AD7740 SPECIFICATIONS
K, Y Versions
1
Parameter
2
Min Typ Max Unit
Test Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
CLKIN = 32 kHz
3
?.012 % of Span
4
Unbuffered Mode, External Clock at CLKIN
CLKIN = 1 MHz
?.012 % of Span Unbuffered Mode, Crystal at CLKIN
CLKIN = 32 kHz
3
?.018 % of Span Buffered Mode, External Clock at CLKIN
CLKIN = 1 MHz
?.018 % of Span Buffered Mode, Crystal at CLKIN
Offset Error
? ?5
mV
Unbuffered Mode, VIN = 0 V
? ?5
mV
Buffered Mode, VIN = 0.1 V
Gain Error
?.1 ?.7 % of Span
Offset Error Drift
3
?0
礦/癈
Gain Error Drift
3
?
ppm of Span/癈
Power Supply Rejection Ratio
3
55
dB
VDD = ?% (5 V)
65
dB
VDD = ?0% (3.3 V)
ANALOG INPUT, VIN
Nominal Input Span
0 V
REF
V
?50 mV Overrange Available
0.1
VDD 0.2 V
Buffered Mode
Input Current
8
10
礎
Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V
5
100
nA
Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V
REFERENCE VOLTAGE
REFIN
5
Nominal Input Voltage
2.5 VDD V
REFOUT
Output Voltage
2.3 2.5 2.7
V
Output Impedance
3
1
k&
See Pin Function Description
Reference Drift
3
?0
ppm/癈
Line Rejection
3
75
dB
VDD = ?% (5 V)
Line Rejection
3
60
dB
VDD = ?0% (3.3 V)
Reference Noise (0.1 Hz to 10 Hz)
3
100
礦 pp
FOUT OUTPUT
Nominal Frequency Span
0.1 f
CLKIN
to 0.9 f
CLKIN
Hz
VIN = 0 V to V
REF
. See Figure 2
LOGIC INPUTS (CLKIN, BUF)
3
CLKIN
Input Frequency
32
1000 kHz
For Specied Performance
Input High Voltage, V
IH
3.5
V
VDD = 5 V ?5%
Input High Voltage, V
IH
2.5
V
VDD = 3.3 V ?10%
Input Low Voltage, V
IL
0.8
V
VDD = 5 V ?5%
Input Low Voltage, V
IL
0.4
V
VDD = 3.3V ?10%
Input Current
?
礎
VIN = 0 V to V
DD
Pin Capacitance
3
10
pF
BUF
Input High Voltage, V
IH
2.4
V
VDD = 5 V ?5%
Input High Voltage, V
IH
2.1
V
VDD = 3.3 V ?10%
Input Low Voltage, V
IL
0.8
V
VDD = 5 V ?5%
Input Low Voltage, V
IL
0.4
V
VDD = 3.3V ?10%
Input Current
?00 nA
Pin Capacitance
3
10
pF
LOGIC OUTPUTS (FOUT, CLKOUT)
3
Output High Voltage, V
OH
4.0
V
Output Sourcing 200 礎
6
. VDD = 5 V ?5%
Output High Voltage, V
OH
2.1
V
Output Sourcing 200 礎
6
. VDD = 3.3 V ?10%
Output Low Voltage, V
OL
0.1 0.4
V
Output Sinking 1.6 mA
6
POWER REQUIREMENTS
V
DD
7
3.0
5.25
V
I
DD
(Normal Mode)
8
0.9 1.25
mA
V
IH
= VDD, V
IL
= GND. Unbuffered Mode
I
DD
(Normal Mode)
8
1.1 1.5
mA
V
IH
= VDD, V
IL
= GND. Buffered Mode
I
DD
(Power-Down)
30 100
礎
Power-Up Time
3
30
祍
Exiting Power-Down (Ext. Clock at CLKIN)
NOTES
1
Temperature range: K Version, 0癈 to +85癈; Y Version, 40癈 to +105癈; typical specications are at 25癈.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
Span = Max output frequencyMin output frequency.
5
Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 礎 in order to overdrive the internal reference.
6
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
7
Operation at VDD = 2.7 V is also possible with degraded specifications.
8
Outputs unloaded. I
DD
increases by C
L
?V
OUT
?f
FOUT
when FOUT is loaded. If using a crystal/resonator as the clock source, I
DD
will vary depending on the crystal/resonator
type (see Clock Generation section).
Specications subject to change without notice.
REV. A
2
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All
specifications T
MIN
to T
MAX
unless otherwise noted.)
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